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| TC6215 www..com N- and P-Channel Enhancement-Mode Dual MOSFET General Description The Supertex TC6215 consists of high voltage, low threshold N-channel and P-channel MOSFETs in an 8-Lead SOIC (TG) package. Both MOSFETs have integrated back to back gate-source Zener diode clamps and guaranteed RDS(ON) ratings down to 4.0V gate drive allowing them to be driven directly with standard 5.0V CMOS logic. These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Features Back to back gate-source Zener diodes Guaranteed RDS(ON) at 4.0V gate drive Low threshold Low on-resistance Independent N- and P-channels Electrically isolated N- and P-channels Low input capacitance Fast switching speeds Free from secondary breakdowns Low input and output leakage Applications High voltage pulsers Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interfaces Ordering Information Package Option Device 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch BVDSS/BVDGS N-Channel (V) RDS(ON) N-Channel () (Max) 8-Lead SOIC P-Channel (V) P-Channel () TC6215 TC6215TG-G 150 -150 4.0 7.0 -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Gate-to-source voltage Operating and storage temperature Soldering temperature* Value BVDSS BVDGS 20V -55C to + 150C 300C Pin Configuration DP DN DN DP 8-Lead SOIC (TG) (top view) SN SP GN GP Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. Product Marking C6215 YYWW LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging Package may or may not include the following marks: Si or 8-Lead SOIC (TG) 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com TC6215 www..com N-Channel Electrical Characteristics (T = 25C unless otherwise specified) A Sym BVDSS VGS(th) VGS(th) VZGS IDSS Parameter Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate-source back to back Zener voltage Zero gate voltage drain current Min 150 1.0 14 560 - Typ 2.0 3.8 120 33 11 2.5 2.3 17.2 11.3 90 Max 2.0 -4.5 25 5.0 1.0 4.0 5.0 4.0 1.0 1.4 - Units V V mV/OC V A mA A Conditions VGS = 0V, ID = 1.0mA VGS = VDS, ID =1.0mA VGS = VDS, ID = 1.0mA IGS = 1.0mA VGS = 0V, VDS = Max Rating VDS = 0.8 Max Rating, VGS = 0V, TA = 125C VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.0V, ID = 0.5A VGS = 5.0V, ID = 2.0A VGS = 10V, ID = 2.0A VGS = 5.0V, ID = 2.0A VDS = 10V, ID = 0.5A VGS = 0V, VDS = 25V, f = 1.0MHz ID(ON) On-state drain current RDS(ON) RDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr Static drain-to-source on-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Diode forward voltage drop Reverse recovery time %/OC mmho pF ns VDD = 25V, ID = 1.0A, RGEN = 25 VGS = 0V, ISD = 0.5A VGS = 0V, ISD = 0.5A V ns Notes: 1. All DC parameters 100% tested at 25C unless otherwise stated. (Pulsed test: 300s pulse at 2% duty cycle.) 2. All AC parameters sample tested. N-Channel Switching Waveforms and Test Circuit 10V Input 0V 10% t(ON) td(ON) VDD Output 0V 90% 90% 10% tr t(OFF) td(OFF) tf 10% Input 90% Pulse Generator RGEN VDD RL OUTPUT D.U.T. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 TC6215 www..com P-Channel Electrical Characteristics (T = 25C unless otherwise specified) A Sym BVDSS VGS(th) VGS(th) VZGS IDSS Parameter Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate-source back to back Zener voltage Zero gate voltage drain current Min -150 -1.0 14 290 - Typ -1.5 -3.0 127 29 9.0 2.4 2.3 16.2 11.1 80 Max -2.0 4.5 25 -5.0 -1.0 7.5 9.0 7.0 1.0 -1.4 - Units V V mV/OC V A mA A Conditions VGS = 0V, ID = -1.0mA VGS = VDS, ID =-1.0mA VGS = VDS, ID = -1.0mA IGS = 1.0mA VGS = 0V, VDS = Max Rating VDS = 0.8 Max Rating, VGS = 0V, TA = 125C VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.0V, ID = -0.25A VGS = -5.0V, ID = -1.0A VGS = -10V, ID = -2.0A VGS = -5.0V, ID = -0.25A VDS = -10V, ID = -0.25A VGS = 0V, VDS = -25V, f = 1.0MHz ID(ON) On-state drain current RDS(ON) RDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr Static drain-to-source on-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Diode forward voltage drop Reverse recovery time %/OC mmho pF ns VDD = -25V, ID = -1.0A, RGEN = 25 VGS = 0V, ISD = -0.25A VGS = 0V, ISD = -0.25A V ns Notes: 1. All DC parameters 100% tested at 25C unless otherwise stated. (Pulsed test: 300s pulse at 2% duty cycle.) 2. All AC parameters sample tested. P-Channel Switching Waveforms and Test Circuit 0V Input -10V 90% t(ON td(ON) 0V Output VDD ) 10% Pulse Generator RGEN t(OFF) tr 90% 10% td(OFF) 90% 10% RL VDD tf Input OUTPUT D.U.T. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 TC6215 www..com Block Diagram SN 1 GN 2 SP 3 8 DN 7 DN 6 DP N-Channel GP 4 P-Channel 5 DP 8-Lead SOIC (top view) Typical Performance Curves P-Channel Output Characteristics -4.0 VGS=-10V -3.5 VGS =-8V VGS=-7V -3.0 -2.5 VGS=-5V N-Channel Output Characteristics 4.5 4.0 3.5 3.0 VGS =10V VGS =8V VGS =7V VGS =6V ID (amperes) VGS=-6V ID (amperes) 2.5 2.0 1.5 1.0 VGS =5V -2.0 -1.5 -1.0 VGS =4V VGS=-4V VGS=-3V -0.5 0.0 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 VGS=-2V -50 VGS =3V 0.5 0.0 0 5 10 15 20 25 30 35 40 45 50 VGS =2V VDS (volts) VDS (volts) P-Channel Saturation Characteristics -2.2 -2.0 -1.8 -1.6 N-Channel Saturation Characteristics 4.0 VGS=-10V VGS=-8V VGS=-6V VGS=-5V 3.5 VGS=10V VGS=8V VGS=6V 3.0 ID (amperes) -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 VGS=-4V ID (amperes) -1.4 2.5 VGS=5V 2.0 VGS=4V 1.5 VGS=-3V 1.0 VGS=3V 0.5 VGS=-2V 0.0 -10 VGS=2V 0 1 2 3 4 5 6 7 8 9 10 VDS (volts) VDS (volts) 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 TC6215 www..com 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch D 8 E E1 Note 1 (Index Area D/2 x E1/2) L2 Gauge Plane 1 1 L L1 Seating Plane Top View A Note 1 View B View B h Seating Plane h A A2 A1 e b Side View A View A-A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A1 A2 b D E E1 e h L L1 L2 1 Dimension (mm) MIN NOM MAX 1.35* 1.75 0.10 0.25 1.25 1.65* 0.31 0.51 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* 1.27 BSC 0.25 0.50 0.40 1.27 1.04 REF 0.25 BSC 0O 8O 5O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version H101708. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. (c)2008 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TC6215 A122208 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 |
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